The invention relates to the field of memory devices used in computer systems, and in particular to large capacity memories.
The memory capacity requirements of computer systems are growing continuously. In many cases, the available space must be as small as possible. These requirements have led to unitary components of ever greater integration being developed: in 1990, the capacities of read/write randomly accessible memory (RAM) components had reached 1 Mbit for static RAM and 4 Mbits for DRAMS. They have also led to interconnection methods enabling chips to be mounted at high densities. To further increase the capacity in a given volume, memory modules have been proposed comprising a stack made up of a plurality of superposed chips on an interconnection substrate. Chips are thus distributed in three dimensions instead of being distributed in a plane only. Unfortunately, problems have been encountered with chip interconnection and above all with connections between the chips and the substrate that give rise to iterative processes that are expensive and lengthy. Because the chips are superposed exactly, it is necessary to make connections to the lower most chip, then to install a spacer, bond the next chip up, wire this new chip, and so on.
Proposals have also been made (Patent Abstracts of Japan, Vol. 11, No. 148, E 506, May 14, 1987) and JP-A-61 287 133 to make a stack comprising a plurality of chips, namely a mass memory, a processor, and a program memory. These chips are of decreasing size going from the substrate to the last chip which is the program memory. The program memory which is smaller than the others is placed transversely to the other two chips which are elongated in the same direction. Because of the different dimensions of the three chips, they can be interconnected. That is not the object of the present invention which seeks to facilitate interconnecting the substrate and the various same-sized memories of a memory module.